What is a pdp8? |
|
|
The digital equipment corporation pdp8 is a programmable data processor with 12bit words and is the "(first) minicomputer".
Although the sentence "first minicomputer" isn't 100 percent correct, it is the pdp8, which had embossed the word "minicomputer". DEC choose the name pdp (programmed data processor) to avoid the association with the unaffordable computers of IBM or Univac.... The pdp8 had very few registers, the program counter (PC), the accumulator (AC), and in later implementations the multiplier quotient register (MQ). The instruction set was simple but complete. A total of only 8 instruction groups were implemented, but 2 of them operate (OPR) and input-output-transfer (IOT) consisted of a lot of different instructions. The rest of the instruction set is so minimalistic, that you are tempted to call it a RISC machine. But exactly these so called memory reference instructions aren't RISC like - as their name says it - too much memory references. ;-) The memory capacity was also very small. Basic installations had 4K 12bit words and maximum installations usually had 32K 12bit words. In the end (pdp8/a) there were installations with up to 128K words. The memory was magnetic core memory, at least up to pdp8/e, pdp8/f, and pdp8/m. The pdp8 was built from 1965 to 1990 in various implementations - from discrete diode transistor logic to TTL ICs to CMOS semiconductors (6100, 6120). Counting the almost compatible pdp5 the time frame begins back in 1963. |
| Date | Version | Cycles | Implemtation | Highlights |
| 1963/08/11 | pdp5 | 12.0 µs | DTL, discrete, transistors in metal cans | wire wrapped backplane => fixed slots for FlipChips |
| 1965/03/22 | pdp8 | 1 - 3 cycles at 1.5 - 1.6 µs | DTL, discrete, transistors in plastic case | wire wrapped backplane |
| 1966 | pdp8/s | 2/1 - 5/5 cycles processor 9.8 and 10.5 µs / memory 6.3 and 6.5 µs | DTL, discrete | wire wrapped backplane, serial ALU (only 1 bit adder), processor and memory don't work synchronous, processor cycle stops while memory access, slowest pdp8 |
| 1968 | pdp8/i, pdp8/l |
1 - 3 cycles at 1.5 µs | TTL, ICs (SN74...) | wire wrapped backplane |
| 1970, 1972, 1972 |
pdp8/e, pdp8/f, pdp8/m |
1 - 3 cycles at 1.2 and 1.4 µs | TTL, MSI ICs (SN74...) | Omnibus => bus backplane, theorectical every expansion card could occupy any slot in the Omnibus, restricted only by timing and noise problems, fastest pdp8, pdp8/e is the most expandable pdp8 |
| 1975 | pdp8/a | 1 - 3 cycles at 1.5 µs | TTL, LSI ICs (SN74...) | Omnibus, ALU uses 3 SN74181, largest memory capabilities |
| 1978 | VT78 | about 2.5 MHz, more cycles / instruction | CMOS, 6100 | pdp8 on microchip build into case of a VT52 terminal, slower than a pdp8 (except the pdp8/s) |
| 1980 | DEC Mate I to III+ | about 8 MHz, more cycles / instruction | CMOS, 6120 | pdp8 on microchip in a modern PC-like terminal case, sold as text editing system, roughly same speed as a pdp8 |